Low Power VLSI Design | Interview Question #01| Dynamic Power Optimization
A.It is the delay between the clock source and clock pin.It is two types.Clock source latency and clock network latency.The time taken from clock source to definition pin is the clock source latency and from the clock definition pin to clock pin of the flip flop 2 is the clock network latency.
A.If we have positive slack use HVT cells in the path and use LVT cells in the path when we have negative slack.HVT cells have large delay and less leakage power. LVT cells have less delay and more leakage power.To meet the timing use LVT cells and to reduce the leakage power use HVT cells.
A. It can be created in RTL by introducing drivers of same or different signal strengths.However during a net with multiple signals are not considered as a good practice.This could lead to failure in a post silicon verification as the driver strength can potentially get heavily altered during manufacturing defects.Many EDA tools dont allow multi driven nets in the design and the designers are expected to remove all multi driven nets from the design.
A. To improve the timing for the design or to improve the congestion for a complex floor plan we can use magnetic placement to specify fixed objects as magnets and icc moves their connected standard cells close to them.For the best results perform the magnetic placement before standard cells are placed.
A. The std-cells in the design are placed in rows.All rows have equal height and spacing.The width of the row can vary.The std-cell in the row get the power and ground connection from vdd and vss rails.Sometimes technology allows the rows to be flip.So they can share the power and ground rails in vdd-vss-vdd patron.
The need for Low Power Design
Companies are continuing to push the boundaries on new features and functionality, all packed into portable, handheld, and battery powered devices. For such products, improving the battery life by minimizing power consumption is a huge differentiator and extremely important to their end users’ applications. Improving the time it takes for a device to go from OFF/SLEEP state to ON/ACTIVE state is just as important, as the end user wants to have a seamless experience along with longer battery life.
For “plug-in” products, power consumption is also important because it can affect the overall cost of systems by requiring heat sinks and elaborate cooling systems, increasing electricity costs, etc. For example, in server farms, where massively parallel systems are used, a reduction in power for a single chip can result in significant power savings because it is used throughout the system. The power and cost savings by upgrading these systems with newer and more power efficient ICs can be significant.
Low Power Design Techniques
There are many low power design techniques available, some of which are very simple to use while others are more involved and complex.
Clock Gating
This technique is typically performed during logic synthesis where enable flops are optimized into a clock gating structure, thereby saving mux area and reducing the overall switching activity of the clock net (refer to Figure 2). With respect to the power equation, the goal is to reduce capacitive load (via area reduction) and activity factors which reduces the switching power component of dynamic power. This is a very simple and readily available technique to reduce power and area. However, it does rely on the logic synthesis tool to perform this optimization. Fortunately, this technique is well-known and well supported in most tools and flows.
Multi Voltage
This is a technique where functions of a chip are partitioned via performance characteristics – perhaps one block is high performance, while the rest of the chip is lower performance as shown in Figure 3. To achieve the goals for the high-performance block, a higher voltage is typically required; while to save power on the lower performance blocks, a lower voltage can be used. This is in lieu of designing the entire block at the higher voltage, which is simpler but more power intensive. In the power equation, voltage is reduced which decreases every static and dynamic power component. With multi voltage designs, there is the complication of designing in separate voltage islands where voltage crossings between islands may require “Level Shifter” (LS) cells with the need to implement and analyze the blocks at their different voltage characteristics.
Power Gating
This is a technique where functions on an IC are also partitioned, much like multi voltage, but this time the power supplies for the power domains are connected to power switches as shown in Figure 4. Power gating effectively shuts off the power completely for a block. In the power equation, this zeros out the voltage and shuts off power, resulting in both static and dynamic savings for the time that the block is turned off. Power gating typically offers the most aggressive power savings, and thus it’s an ideal goal to shut off as many domains as possible, as often as possible, while maintaining functionality. In order to achieve this power savings with power gating, power switches must be implemented in the design, which requires Isolation gates that clamp the boundaries of the power domain to known values when off. The power states of the design and what combination of ON/OFF states for given voltages must be considered. Lastly, a power management unit (PMU) that controls the power switch and isolation enable signals must be implemented. It is essential that the order of these signals are correct during power down and power up, such that the values during shutdown are clamped to the right values at the right time.
Retention with Power Gating
Retention (or register retention) is a technique used along with power gating. Here in each shutdown block, when the block is OFF, either a subset of the flops or all the flops in the block have their previous values saved. When the block powers on, then the previously saved values will be restored. It is important to save the state of the block at the time it is powered off so that the block can quickly restore its previous state instead having to cycle through from an INIT state to the current state. This saves power by reducing the time and steps necessary to get the saved state, as well as improves the overall ramp up time to restore the previous functionality of the block. In addition to everything needed for power gating, retention flops must exist in the library that can map to the desired registers in the RTL. SAVE/RESTORE signals will need to be added to the PMU along with the control the sequence of these signals in addition to those done for power gating (refer to Figure 5).
Advanced Techniques
There are many more advanced techniques for low power design, including the combination of the techniques previously mentioned. Blocks that use a lower voltage with power gating and have isolation, retention, and level shifters are commonly seen in many modern-day chips. Well biasing, zero-pin retention flops, specialized low power library cells, dynamic voltage and frequency scaling (DVFS), adaptive voltage and frequency scaling (AVFS), and custom design are just some of the other advanced low power techniques also used in the industry.
FAQ
What questions should a design engineer ask?
- “Where do you find inspiration?” …
- “How did you design your portfolio?” …
- “Tell me about the projects you’re most proud of and why. …
- “What software do you use?” …
- “How do you work cross-functionally with developers, copywriters, project managers, etc.?”
What are the interview questions for mechanical design engineer?
- What important details should be on a new product blueprint? …
- How do you ensure you keep up-to-date with the latest engineering trends and techniques? …
- What design software do you use and why? …
- Can you describe your method for explaining complex engineering designs to clients?
