- How AHB is pipelined architecture?
- What is the size of the max data that can be transferred in a single transfer?
- Explain the 1k boundary concept in AHB?
- Okay, response is a single cycle? …
- Explain the concept of a two-cycle response?
- What if the slave gets the address out of range?
AHB DEMO SESSION
Are you an engineering graduate with good command on technical skills? Are you a person willing to work in different environment then log on to www.wisdomjobs.com. AMBA AHB Advanced Microcontroller Bus Architecture is an open standard, on chip interconnect specification for the connection and management bid functional blocks in system on chip (SoC) designs. It facilities development of multiprocessor designs with large numbers of controllers and peripherals. AHB is Advanced High PerformanceBus and is part of AMBA, transfer can start with the bus master, by asserting a request signal to the arbiter. Then the arbiter when the master will be granted to use the bus. A granted Master bus starts the transfer with address and control signal. So track your future as Soc Verification Engineer, Digital Verification Engineer, Senior Silicon Engineer, lead IP Engineer and so on by looking into AMBA AHB job interview question and answers given.
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HOME SYSTEMVERILOG Search UVM SYSTEMC ASIC SLIDES Tutorials SystemVerilog Tutorial SystemC Tutorial AMBA AHB AXI Interview Questions UVM Tutorial SystemVerilog Quiz AHB Interview Questions SystemC Quiz Interview Questions 1. How AHB is pipelined architecture? 2. What is the size of max data can be transferred in single transfer? SystemVerilog Interview Questions 3. Explain 1k boundary concept in AHB? UVM Interview Questions 4. Okay response is single cycle? but error/split/retry is two cycle, why? SystemC Interview Questions 5. Explain the concept of two cycle response? ASIC Verification Interview Questions 6. What if the slave gets the address out of range? SOC Verification Interview Questions 7. How to connect multiple slaves to single master? AMBA AHB AXI Interview Questions 8. Explain the round robin arbitration concept? Contact / Report an issue 9. Explain the splitretry concept? 10. What is the difference between HREADY and HREADY_OUT signals? 11. What is the slave response for BUSY transfer? 12. What is the difference between WRAP4 and INCR4? 13. How to terminate the INCR type transfer? 14. What is difference between BURST and Beat? 15. How to calculate the size of the burst? 16. Is HREADY is Input or output to/from the slave? 17. What is align and unalign concept? 18. Explain wrapping calculation? 19. Is early burst termination is done by Slave/Arbiter? 20. Explain the LOCKED transfer? 21. What is default Master? 22. What is littleendian and bigendian? 23. How slave will detects the end of INCR type burst transfer? AXI Interview Questions 1. How AXI is different from AHB? 2. Explain the concept of AXI 4KB boundary condition? 3. Explain the valid ready handshake in AXI? 4. Explain the channel concept? 5. Explain the outoforder concept? 6. What is fixed burst type? 7. Explain the AXI response types? Recommend this on Google © Copyright 2016 Verification Guide. All rights reserved. Your valuable inputs are required to improve the quality. Follow Us
FAQ
How many slaves can be connected to AHB?
What is AHB protocol?
What is Pipelining in AHB?
Why is APB bridge to AHB?
