Understanding Logic Equivalence Check in VLSI | What is LEC?
Steps for Logical Equivalence Checks
Let’s take a close look at the various steps of logical equivalence checks:
In the setup mode, the Conformal tool reads two designs. We designate the design types, which are Golden (synthesized netlist) and Revised (generally, the revised design is the modified or post-processed design that the Conformal tool compares to the Golden design). For the execution of LEC, the Conformal tool requires three types of files.
In the transition from setup mode to LEC mode, the Conformal tool flattens and models the golden and revised designs and automatically maps the key points. The key points are defined as:
During the second phase of equivalence checking, the Conformal tool automatically maps key points and compares them. When the comparison is complete, it pinpoints the differences. The Conformal tool employs two name-based methods and one no-name method to map key points. Name-based mapping is useful for gate-to-gate comparisons when minor changes have been made to the logic.
Conversely, the no-name-mapping method is useful when the Conformal tool must map designs with completely different names. By default, it automatically maps key points with the name-first mapping method when it exits the setup mode. The key points that the Conformal tool does not map are classified as unmapped points.
Unmapped points are classified into three categories:
After the Conformal tool maps the key points, the next step of the verification is comparison. Comparison examines the key points to determine if they are equivalent or non-equivalent. The comparison determines if the compared points are:
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In the case of aborted compare points, we can change the compare effort to a higher setting. Thus, the Conformal tool can continue the comparison on only the aborted compare points. The Conformal tool displays the completed run time and total memory used for the comparison.
Multiple reports are generated once LEC is completed:
At the time of sign-off or tapeout phase, the schedule is too tight to handle blocks with some critical logical failure. At times, the logical connectivity is broken while doing manual fixes or timing ECOs. The chances of a logical breakdown will be high at the tapeout phase where the physical design engineer does not have much time for block closure. Also, the chances of breaking logical connectivity are high, when you get the functional ECO and do the manual connection. Let’s take a look at a practical example of LEC failure in a block and see how it can be solved.
First of all, do not panic if LEC fails during any of the levels, discussed earlier. When LEC is failing, the first step is to check the “non-equivalent.rpt” file. It may be possible that due to one broken connection, a higher number of cell names are reported in the “non-equivalent.rpt” file.
The reason behind is that many paths which are going through one failed/broken connection – and hence all its endpoints (compare points) – are reported “Non-equivalent”.
The first step is to check the non-equivalent file. The sample non-equivalent file below shows the 152 compare points that are failing in in LEC.
These 152 flip-flops reported as non-equivalent are the multibit flops. In multibit flops, we merge two flops to form a single flop having multiple input and output pins. For example, if we merge two single bit flops into one multibit flop, it will have D0, D1 as input pins and Q0, Q1 as output pins.
Because of multibit flops, the report is showing 152 flop count as non-equivalent, but actually only 72 are non-equivalent. As these are two bit flops, the total count is 72×2=144 flops. The remaining are single bit flops.
Next step is to check the unmapped file. This file shows the unmapped nets where the logical connectivity is broken. We need to trace nets and find out the missing connection of those nets.
In the above , we can see that one net (BUFT_net_362908) is not mapped in the design. As it can be seen in Fig-2, once we check this net (BUFT_net_362908) connection in LEC fail database, we see that it is connected only to the input pins of other cell (*_364714/A), but the other connection (driver side) of this net is missing due to unintentional cell deletion.
The highlighted net in the below figure shows the net reported in the unmapped.rpt file.
Here, we can see the connection of reported net in the LEC fail design.
While we do the fanout of net (BUFT_net_362908) which is reported in unmapped file, it is connected to 152 flops in LEC pass database.
Whereas 152 flops reported in non-equivalent file in LEC fail database are same as fanout of net (BUFT_net_362908) reported in LEC pass database.
Now, we need to find the actual net connection of this net in the previous LEC pass database. While checking, we can easily note that the reported net is connected to one inverter which is missing in the LEC fail database.
For finding the missing cell, we have to back trace this net in the previously LEC passed database and check actual connections.
Do not get confused between un-mapped and non-equivalent reports. In the un-mapped report we only see the floating nets of the undriven input pins, whereas in the non-equivalent report we see all the cells which are fanouts of this missing cell.
After finding the reason for the LEC failure, we have to insert one missing inverter and redo the input/output logical connection of this inverter in the LEC failed database. Fig-3 shows the newly added inverter and its input-output connection. Now, if we rerun the LEC it will pass and non-equivalent report will show zero non-equivalent points.
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Once the netlist gets generated it is must to ensure that its functionality is equivalent to the RTL design from which it has been generated. The logical equivalence check performed to ensure the logical equivalency of the gate level Netlist with the RTL design. It can also be performed to check the equivalence of the:
Most of the challenges and the problems are faced in the process are due to logic optimization at the Synthesis stage. The netlist generated during the Synthesis process is finalized after number of process iterations to meet the Timing and Design constraints. These optimizations involves in removing of unused sequential elements and also merging of the sequential elements. As in comparison to the RTL, the netlist can posses different properties if it get generated with clock gating or scan enable sequential elements. One must be look after these main points while doing formal verification:
Logic Equivalence Check: ASIC design cycle involves a number of stages that vary from functional design to its verification at different levels. As soon as the design is completed and verified through different methodologies is ready to go to a semiconductor chip. Hold on, it’s not simple as it said, one of the most crucial steps is involved while taking RTL design to the chip level. Synthesis, which involves the conversion of RTL design to the equivalent gate-level netlist. This netlist is then used for the physical design implementation.
A number of EDA companies provide equivalency check tools out of them Formality (Synopsys) and Conformal (Cadence) and mostly used at the industry level.
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